- Job Type: Full-Time
- Function: Engineering Hardware
- Industry: Semiconductors
- Post Date: 04/27/2021
- Website: neuroblade.ai
- Company Address: Tel Aviv-Yafo
About NeuroBladeFast general purpose AI execution with no memory bottlenecks and no accuracy compromises.
NeuroBlade is looking for a Senior Chip Design Engineer to join our fast-growing engineering team. We are looking for brilliant and passionate people to join us and play a major role in building the next big thing in AI! If you enjoy working on cutting edge technologies and solving complex problems, and have team spirit and a can-do-attitude – Your place is with us!
Founded in 2017, NeuroBlade set out on a mission to redefine computer architecture for AI and other memory intensive tasks. We build high performance solutions for the rapidly growing AI market while lowering costs and power usage. NeuroBlade’s unique hardware solution paired with a complete end-to-end SW stack, enables businesses to take the next leap forward by increasing the efficiency and affordability of their devices from edge devices to datacenters.
NeuroBlade’s state of the art AI compiler is a complex software that requires our engineers to solve difficult problems in low and high level optimization, data-science, graph theory, linear algebra and more.
WHAT YOU’LL BE DOING
Design, review and deploy complex blocks & modules
Guide and review the work of your team members
Participate in the definition and implementation of advanced computer architecture
Help bring your design to a full product inside a real system
5+ years experience in chip design
5+ years experience and deep knowledge of Verilog & system Verilog
Experience in writing SVA assertions
Scripting knowledge – Perl, Python, TCL, etc.
Experience with synthesis results analysis and timing closure process
Understanding advanced verification methods and experience with the coverage closure process
Electronics Engineering degree from a leading institute, graduation with honors
Knowledge in AI/ML
Experience with VLSI backend methodologies & tools
Experience with SV UVM verification environments