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Senior Chip Backend Design Engineer

NeuroBlade

Ramat HaHayal, IL
  • Job Type: Full-Time
  • Function: Engineering Hardware
  • Industry: Semiconductors
  • Post Date: 01/06/2021
  • Website: neuroblade.ai
  • Company Address: Tel Aviv-Yafo

About NeuroBlade

Fast general purpose AI execution with no memory bottlenecks and no accuracy compromises.

Job Description

NeuroBlade is looking for a Senior Chip Backend Design Engineer to join our fast-growing engineering team. We are looking for brilliant and passionate people to join us and play a major role in building the next big thing in AI! If you enjoy working on cutting edge technologies and solving complex problems, and  have  team spirit and a can-do-attitude – Your place is with us!

Founded in 2017,  NeuroBlade set out on a mission to redefine computer architecture for AI and other memory intensive tasks. We build high performance solutions for the rapidly growing AI market while lowering costs and power usage. NeuroBlade’s unique hardware solution paired with a complete end-to-end SW stack, enables businesses to take the next leap forward by increasing the efficiency and affordability of their devices from edge devices to datacenters.

WHAT YOU’LL BE DOING

Be involved in challenging backend activities
Work closely with the architecture and design teams
Leading role in defining & developing innovative methodologies and infrastructure
Participate in the entire flow, starting from synthesis up to sign-off, macro and fullchip levels
Guide and review the work of your team members

REQUIRED

5+ years experience in a chip backend design proficiency in scripting
5+ years experience and deep knowledge with all stages of the backend flow, from synthesis to sign-off
Experience in definition and implementation of methodologies & tools
Experience in collaboration with the FE team to solve issues
Electronics engineering degree from a leading institute, graduation with honors

BONUS

Experience in implementations of methodologies & tools
Experience with Cadence BE tools (Genus, Innovus, Tempus, etc.)
Experience with power analysis tools (Redhawk, Voltus)
Knowledge of DFT
Experience in chip design