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Design Verification Engineer


Yoqneam, IL
  • Job Type: Full-Time
  • Function: Engineering QA
  • Industry: Semiconductors
  • Post Date: 05/12/2021
  • Email: careers@ramon.space
  • Website: www.ramon.space
  • Company Address: Palo Alto

About Ramon.Space

Ramon.Space is bringing super computing to space!

The company develops hardware and software computing systems for the rising demands of ‘New Space’ players.

Quickly and cost effectively deploy space-resilient payloads such as earth observation, communications, networking and more, using technology already used in hundreds of units in space.

Job Description


We are expanding our Design Verification team, and invite you to explore Space with us!

The job includes taking viable role in the VLSI verification tasks of Ramon.Space line of products.

Job description

  • Definition of the DV plan including DV requirements, Architecture, Test plan and deliverables.

  • Implementation of UVM / DVE components.

  • Conduct status and progress review 

  • Take part of Block level to full chip/FPGA level DV, Includes Debug and GLS.

  • Develop Scripts in various scripting languages for supporting the DV / VLSI automation.

  • Proficient English​

Must have

  • Experienced Design Verification Engineer with Solid DV background.

  • Hands on with Definition and Execution of DV Test benches in UVM, System Verilog.

  • Hands on and ownership of DV module verification from definition to Signoff.

  • Solid knowhow of ASIC and FPGA design flow.

  • Solid knowhow in Digital System Design.

  • Independent, Team Player with good team spirit, a Must.