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Junior Verification Engineer


Ramat HaHayal, IL
  • Job Type: Full-Time
  • Function: Engineering QA
  • Industry: Semiconductors
  • Post Date: 06/07/2021
  • Website: neuroblade.ai
  • Company Address: Tel Aviv-Yafo

About NeuroBlade

Fast general purpose AI execution with no memory bottlenecks and no accuracy compromises.

Job Description

NeuroBlade is looking for a Verification Engineer to join our fast-growing engineering team.
We are looking for brilliant and passionate people to join us and play a major role in building the next big thing in big data computing! If you enjoy working on cutting edge technologies, solving complex problems, have a team spirit and a can-do-attitude – Your place is with us!

NeuroBlade is on a path to redefine an industry held back by the inability to analyze data in the speed and scale needed. We design a complete multidisciplinary solution for Data Analytics acceleration.

NeuroBlade was established in 2018 with the stated goal of enabling faster time to insights by freeing analytics from data movement constraints. It led to the creation of a whole new memory technology, XRAM™, that radically improves performance. 

In 2020, NeuroBlade introduced the IMPU™ (Intense Memory Processing Unit), a hardware accelerator for data-driven workloads, which has set a new standard in query processing.

We’ve only just begun.

What you’ll be doing:

  • Design, review and deploy UVM-based verification environments in block, chip, and system levels.
  • Verify the design and hunt for bugs, working closely with other teams.
  • Build sophisticated, automated & randomized environments to cover all corners of the design.
  • Use state of the art verification tools and technologies.
  • Enhance the verification cycle-time by building automation infrastructure.


  • BSC EE-engineer/Computer-science, GPA 85 or above
  • 1-3 years of hands-on chip verification experience
  • Scripting knowledge: Python/TCL/Perl
  • A team player, quick learner, good multitask ability, self-managed.


  • Knowledge with UVM
  • Experience with RTL design, SystemVerilog
  • Knowledge with industry protocols such as AXI, Pcie, DDR